Table 1
Resource usage of the F-engine.
| Module | LUTs | FFs | BRAM | URAM | DSPs | Power (W) | DDR4 (GB/s) |
|---|---|---|---|---|---|---|---|
| FIR | 9676 | 4922 | 52 | 0 | 65 | 0.5 | — |
| FFT | 18 147 | 25 554 | 4 | 0 | 63 | 2.4 | — |
| Coarse delay corrector | 556 | 911 | 32 | 0 | 0 | 0.1 | — |
| Fine delay corrector | 2570 | 8427 | 4 | 0 | 56 | 0.1 | — |
| Corner turner | 15 566 | 21 860 | 24 | 32 | 0 | 1.1 | 8.192 |
| Network | 25 089 | 33 375 | 83 | 0 | 0 | 3.9 | — |
| Total a | 260291 | 367971 | 765 | 32 | 750 | 30.0 | 8.192 |
| Available | 425 280 | 850 560 | 1080 | 80 | 4272 | — | 10.664 b |
| Percentage | 68% | 42% | 74% | 40% | 26% | — | 77% |
Notes. The resource usage for the FIR, FFT, coarse delay corrector, and fine delay corrector is measured per data stream. Since there are four data streams in total, the overall resource consumption scales accordingly. (a) The total resource usage and power consumption include all modules not listed in the table. (b) The theoretical DDR4 bandwidth is based on a clock frequency of 1333 MHz. However, experimental tests show a maximum achievable throughput of only 8.7 GB/s.
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